View AK4351_464658.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ASAHI KASEI
[AK4351]
18Bit Advanced Multi Bit DS 2ch DAC
AK4351
GENERAL DESCRIPTION The AK4351 is a high cost performance 18bit stereo DAC for low-end digital audio systems. The modulator in the AK4351 uses the new developed Advanced Multi Bit architecture with wide dynamic range. The analog outputs are filtered in the analog domain by a combination of SCF and CTF. Therefore, any external filters are not required. The SCF techniques also improve the loss of accuracy from clock jitter. Therefore, the AK4351 is suitable for the system like STB including PLL circuit. The AK4351 is available in very small 16pin TSSOP package, which reduces system space. FEATURES * Sampling Rate Ranging from 8kHz to 50kHz * 128 times Oversampling * Perfect filtering 18bit 8 times FIR Interpolator with 57dB attenuation 2nd order LPF Total Response: 0.2dB at 20kHz * On chip Buffer with Single End Output * Digital de-emphasis for 44.1kHz sampling * I/F format: MSB justified, 16/18bit LSB justified or I2S * Master clock: 256fs or 384fs * TTL Level Digital Interface * THD+N: -88dB * D-Range: 96dB * High Tolerance to Clock Jitter * Power supply: 4.5 to 5.5V * Very Small Package: 16pin TSSOP (6.4mm x 5.0mm)
DIF0 DIF1 DEM MCLK CKS TST
De-emphasis Control
LRCK BICK SDATA VDD VSS
Serial Input Interface
Clock Divider
VCOM
8X Interpolator 8X Interpolator
DS Modulator DS Modulator
LPF
AOUTL
LPF
AOUTR
PD
VREF
M0022-E-04 -1-
1999/12
ASAHI KASEI
[AK4351]
n Ordering Guide
AK4351VT AKD4351 -40 ~ +85C 16pin TSSOP (0.65mm pitch) Evaluation Board for AK4351
n Pin Layout
DIF1 LRCK BICK SDATA PD MCLK DEM CKS 1 2 3 4 5 6 7 8 16 15 14 DIF0 VSS VDD VREF VCOM AOUTL AOUTR TST
Top View
13 12 11 10 9
PIN/FUNCTION
Function Digital Input Format Pin (Internal Pull-down pin) L/R Clock Pin Audio Serial Data Clock Pin Audio Serial Data Input Pin Power-Down Mode Pin PD When at "L", the AK4351 is in power-down mode and is held in reset. The AK4351 should always be reset upon power-up. 6 MCLK I Master Clock Input Pin An external TTL clock should be input on this pin. 7 DEM I De-emphasis Enable Pin When at "H", de-emphasis of fs=44.1kHz is enabled. 8 CKS I Master Clock Select Pin (Internal Pull-down pin) "L": MCLK=256fs, "H": MCLK=384fs 9 TST O Test Pin Must be left floating. 10 AOUTR O Rch Analog Output Pin 11 AOUTL O Lch Analog Output Pin 12 VCOM O Common Voltage Pin, VDD/2 Normally connected to VSS with a 0.1F ceramic capacitor in parallel with a 10F electrolytic cap. 13 VREF I Voltage Reference Input Pin The differential Voltage between this pin and VSS set the analog output range. Normally connected to VDD. 14 VDD Power Supply Pin 15 VSS Ground Pin 16 DIF0 I Digital Input Format Pin (Internal Pull-down pin) Note: All input pins except pull-down pins should not be left floating. No. 1 2 3 4 5 Pin Name DIF1 LRCK BICK SDATA I/O I I I I I
M0022-E-04 -2-
1999/12
ASAHI KASEI
[AK4351]
ABSOLUTE MAXIMUM RATINGS
(VSS=0V; Note 1) Parameter Power Supply Input Current, Any Pin Except Supplies Input Voltage Ambient Operating Temperature Storage Temperature Note:1. All voltages with respect to ground. Symbol VDD IIN VIND Ta Tstg min -0.3 -0.3 -40 -65 max 6.0 10 VDD+0.3 85 150 Units V mA V C C
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS=0V; Note 1) Parameter Power Supply Voltage Reference Symbol VDD VREF min 4.5 3.0 typ 5.0 max 5.5 VDD Units V V
(Note 2)
Note:2. Analog output voltage scales with the voltage of VREF. AOUT (typ.@0dB)=3.45Vpp*VREF/5.
*AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
M0022-E-04 -3-
1999/12
ASAHI KASEI
[AK4351]
ANALOG CHARACTERISTICS
(Ta=25C; VDD=5.0V; fs=44.1kHz; BICK=64fs; Signal Frequency=1kHz; 18bit Input Data; Measurement frequency=10Hz ~ 20kHz; RL 5kW; unless otherwise specified) Parameter min typ max Resolution 18 Dynamic Characteristics (Note 3) THD+N (0dB Output) -88 -80 Dynamic Range (-60dB Output, A-weight) 90 96 S/N (A-weight) 90 96 Interchannel Isolation (1kHz) 96 100 Interchannel Gain Mismatch 0.2 0.5 DC Accuracy Gain Drift 100 Output Voltage (Note 4) 3.20 3.45 3.70 Load Resistance 5 Output Current 400 Power Supplies Power Supply Current Normal Operation ( PD ="H") VDD Power-Down Mode ( PD ="L") VDD Power Dissipation (VDD) Normal Operation Power-Down Mode Power Supply Rejection (Note 5) 10 70 50 40 50 100 250 A mW W dB 14 20 mA
Units Bits dB dB dB dB dB ppm/C Vpp kW A
(Note 5) (Note 6)
Note: 3. Measured by AD725C (SHIBASOKU). Averaging mode. Refer to the evaluation board manual. 4. Full-scale voltage (0dB). Output voltage scales with the voltage of VREF. AOUT (typ.@0dB)=3.45Vpp*VREF/5. 5. Power Dissipation in the power-down mode is applied with no external clocks (MCLK, BICK and LRCK held "VDD" or "VSS"). 6. PSR is applied to VDD with 1kHz, 100mVpp. VREF pin is held +5V.
M0022-E-04 -4-
1999/12
ASAHI KASEI
[AK4351]
FILTER CHARACTERISTICS
(Ta=25C; VDD=4.5 ~ 5.5V; fs=44.1kHz; DEM="L") Parameter Symbol Digital filter PB Passband 0.05dB (Note 7) -6.0dB Stopband (Note 7) SB Passband Ripple PR Stopband Attenuation SA Group Delay (Note 8) GD Digital Filter + LPF Frequency Response 0 ~ 20.0kHz min 0 24.1 54 typ max 20.0 0.02 19.1 0.2 Units kHz kHz kHz dB dB 1/fs dB
22.05
Note: 7. The passband and stopband frequencies scale with fs. For example, PB=0.4535*fs (@0.05dB), SB=0.546*fs. 8. The calculating delay time which occurred by digital filtering. This time is from setting the 16/18bit data of both channels to input register to the output of analog signal.
DIGITAL CHARACTERISTICS
(Ta=25C; VDD=4.5 ~ 5.5V) Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage (Iout=-80A) Low-Level Output Voltage (Iout=80A) Input Leakage Current (Note 9) Symbol VIH VIL VOH VOL Iin min 2.2 VDD-0.4 typ max 0.8 0.4 10 Units V V V V A
Note: 9. DIF0, DIF1 and CKS pins have internal pull-down devices, normally 100kW.
M0022-E-04 -5-
1999/12
ASAHI KASEI
[AK4351]
SWITCHING CHARACTERISTICS
(Ta=25C; VDD=4.5 ~ 5.5V; CL=20pF) Parameter Master Clock Timing 256fs: Pulse Width Low Pulse Width High 384fs: Pulse Width Low Pulse Width High LRCK Frequency Duty Cycle Serial Interface Timing BICK Period BICK Pulse Width Low Pulse Width High BICK rising to LRCK Edge (Note 10) LRCK Edge to BICK rising (Note 10) SDATA Hold Time SDATA Setup Time Reset Timing PD Pulse Width (Note 11) Symbol fCLK tCLKL tCLKH fCLK tCLKL tCLKH fs Duty tBCK tBCKL tBCKH tBLR tLRB tSDH tSDS tPD min 2.048 28 28 3.072 20 20 8 45 312.5 100 100 50 50 50 50 100 typ 11.2896 max 12.8 Units MHz ns ns MHz ns ns kHz % ns ns ns ns ns ns ns ns
16.9344
19.2
44.1
50 55
Note: 10. BICK rising edge must not occur at the same time as LRCK edge. 11. The AK4351 can be reset by bringing PD = "L". When clocks are changed during the operation, please reset the AK4351 at once by PD = "L".
M0022-E-04 -6-
1999/12
ASAHI KASEI
[AK4351]
n Timing Diagram
1/fCLK VIH VIL tCLKH tCLKL
MCLK
1/fs VIH VIL
LRCK
tBCK VIH VIL tBCKH tBCKL
BICK
Clock Timing
LRCK tBLR tLRB
VIH VIL
BICK tSDS tSDH
VIH VIL
SDATA
VIH VIL
Serial Interface Timing tPD
PD
VIL Power-down
M0022-E-04 -7-
1999/12
ASAHI KASEI
[AK4351]
OPERATION OVERVIEW n System Clock
The external clocks, which are required to operate the AK4351, are MCLK, LRCK and BICK. The master clock (MCLK) should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the delta-sigma modulator. The frequency of MCLK is determined by the sampling rate (LRCK) and CKS pin. Table 1 illustrates corresponding clock frequencies. When the 384fs is selected, the internal master clock becomes 256fs(=384fs*2/3). All external clocks (MCLK, BICK and LRCK) should always be present whenever the AK4351 is in normal operation mode ( PD = "H"). If these clocks are not provided, the AK4351 may draw excess current because the device utilizes dynamic refreshed logic internally. The AK4351 should be reset by PD = "L" after threse clocks are provided. If the external clocks are not present, the AK4351 should be in the power-down mode( PD = "L"). After exiting reset at power-up etc., the AK4351 is in power-down mode until MCLK and LRCK are input. When those clocks are changed during the operation, please reset the AK4351 at once by PD = "L".
Clock LRCK (fs) BICK MCLK CKS = "L" CKS = "H"
frequency 8k ~ 50kHz ~ 64fs 256fs 384fs
Table 1. System Clocks
n Audio Serial Interface Format
Data is shifted in via the SDATA pin using BICK and LRCK inputs. The DIF0-1 pins as shown in Table 2 can select four serial data modes. In all modes the serial data is MSB-first, 2's compliment format and is latched on the rising edge of BICK. Mode 2 can be used for 16MSB justified formats by zeroing the unused LSBs. DIF1 0 0 1 1 DIF0 0 1 0 1 Mode BICK 0: 16bit LSB Justified 32fs 1: 18bit LSB Justified 36fs 2: 18bit MSB Justified 36fs 3: I2S Compatible 36fs or 32fs Table 2. Serial Data Modes Figure Figure 1 Figure 1 Figure 2 Figure 3
LRCK
Lch
Rch
BICK SDATA Mode 0 SDATA Mode 1
Don't care 15:MSB, 0:LSB (@16bit Data) Don't care 17 16 15 14 0 Don't care 17 16 15 14 0 15 14 0 Don't care 15 14 0
17:MSB, 0:LSB (@18bit Data)
Figure 1. Mode 0,1 Timing
M0022-E-04 -8-
1999/12
ASAHI KASEI
[AK4351]
LRCK
Lch
Rch
BICK SDATA 16bit SDATA 18bit
15 14 1 0 Don't care 15 14 1 0 Don't care
15
14
17
16
3
2
1
0
Don't care
17
16
3
2
1
0
Don't care
17
16
Figure 2. Mode 2 Timing
LRCK
Lch
Rch
BICK SDATA 16bit SDATA 18bit
15 14 1 0 Don't care Don't care 15 14 1 0 Don't care 15
17
16
3
2
1
0
17
16
3
2
1
0
Don't care
17
Figure 3. Mode 3 Timing
n De-emphasis filter
The AK4351 includes the digital de-emphasis filter (tc=50/15s) by IIR filter. This filter corresponds to 44.1kHz sampling. Setting DEM pin "H" enables the de-emphasis.
M0022-E-04 -9-
1999/12
ASAHI KASEI
[AK4351]
n Power-down
The AK4351 is placed in the power-down mode by bringing PD pin "L" and the anlog outputs are floating(Hi-Z). Figure 4 shows an example of the system timing at the power-down and power-up.
PD
Internal State D/A In (Digital)
Normal Operation
Power-down
Normal Operation
"0"data GD (1) GD (1) (3) (2) (3)
D/A Out (Analog) Clock In
MCLK,LRCK,BICK
(4)
External Mute
(5)
Mute On
Figure 4. Power-down/up sequence example Notes: (1) Analog output corresponding to digital input has the group delay (GD). (2) Analog outputs are floating (Hi-Z) at the power-down mode. (3) Click noise occures at the edges(" ") of the falling edge of PD signal. (4) When the external clocks(MCLK,BICK,LRCK) are stopped, the AK4351 should be in the power-down mode. (5) Please mute the analog output externally if the click noise(3) influences system application. The timing example is shown in this figure.
n System Reset
The AK4351 should be reset once by bringing PD = "L" upon power-up. The AK4351 is powered up and the internal timing starts clocking by LRCK "" after exiting reset and power down state by MCLK. The AK4351 is in power-down mode until MCLK and LRCK are input.
M0022-E-04 - 10 -
1999/12
ASAHI KASEI
[AK4351]
SYSTEM DESIGN
Figure 5 shows the system connection diagram. An evaluation board [AKD4351] is available in order to allow an easy study on the layout of a surrounding circuit.
Analog 5V
1
DIF1 LRCK BICK SDATA PD MCLK DEM CKS
DIF0 VSS
16 15 14 13 10u 12 11 10 9 + 10u 220 27k + + 10u 220 27k 0.1u 10u +
Decoder
2 3 4
AK4351
Top View
VDD VREF VCOM AOUTL AOUTR TST
Reset External Clock Mode Setting
5 6 7 8
Lch Out
Rch Out
System Ground
Analog Ground
Figure 5. Typical Connection Diagram Notes: - When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive load. - ALL input pins except internal pull-down pins should not be left floating. - Decoupling capacitor, especially 0.1F ceramic capacitor for high frequency should be placed as near to VDD and VREF pins as possible. - System ground including DSP/P should be separated from AK4351's VSS. Both grounds should be connected by one point at power supply or regulator on system board.
M0022-E-04 - 11 -
1999/12
ASAHI KASEI
[AK4351]
1. Grounding and Power Supply Decoupling VDD and VSS are supplied from analog supply and should be separated from system digital supply. Decoupling capacitor, especially 0.1mF ceramic capacitor for high frequency should be placed as near to VDD as possible. 2. Voltage Reference The differential Voltage between VREF and VSS sets the analog output range. VREF pin is normally connected to VDD with a 0.1F ceramic capacitor. VCOM is a signal ground of this chip. An electrolytic capacitor 10F parallel with a 0.1F ceramic capacitor attached to VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from VCOM pin. ALL signals, especially clocks, should be kept away from the VREF and VCOM pins in order to avoid unwanted coupling into the AK4351. 3. Analog Outputs The analog outputs are also single-ended and centered around the VCOM voltage. The output signal range is typically 3.45Vpp. AC coupling capacitors of larger than 1F are recommended. The internal switched-capacitor filter and continuous-time filter attenuate the noise generated by the delta-sigma modulator beyond the audio passband. Therefore, any external filters are not required for typical application. The output voltage is a positive full scale for 7FFFH(@16bit) and a negative full scale for 8000H(@16bit). The ideal output is VCOM voltage for 0000H(@16bit). DC offsets on analog outputs are eliminated by AC coupling since analog outputs have DC offsets of VCOM + a few mV.
M0022-E-04 - 12 -
1999/12
ASAHI KASEI
[AK4351]
PACKAGE
16pin TSSOP (Unit: mm)
*5.0 1.10max
16
9 A 6.40.2 0.170.05 0.10.1 Detail A 0.50.2 1.0 0.10 0-10
Epoxy Cu Solder plate 1999/12 - 13 -
1 0.220.1
8 0.65
Seating Plane
NOTE: Dimension "*" does not include mold flash.
n Package & Lead frame material
Package molding compound: Lead frame material: Lead frame surface treatment:
M0022-E-04
*4.4
ASAHI KASEI
[AK4351]
MARKING
AKM 4351VT XXYYY
Contents of XXYYY XX: Lot# YYY: Date Code
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
M0022-E-04 - 14 -
1999/12

▲Up To Search▲

Price & Availability of AK4351

	To Download AK4351 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .